Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
246
Example 1
If Working Register R3 contains 45h (01000101b) and Working Register R7 contains the
value
02h (00000010b) (bit 1 is being tested if it is 0), the statement:
TM R3, R7
Op Code: 72 37
sets the Z Flag indicating bit 1 in the destination operand is 0. The V and S Flags are
cleared.
Example 2
Working Register R14 contains the value F3h (11110011b), Working Register R5 con-
tains
CBh, and Register CBh contains 88h (10001000b) (bit 7 a bit 3 are being tested if
they are 0), the statement:
TM R14, @R5
Op Code: 73 E5
resets the Z Flag, because bit 7 in the destination operand is not a 0. The S Flag is set, and
the V Flag is cleared.
Example 3
If Register D4h contains the value 08h (00001000b), and Working Register R0 contains
the value
04h (00000100b) (bit 2 is being tested if it is 0), the statement:
TM D4h, R0
Op Code: 74 E0 D4
sets the Z Flag, because bit 2 in the destination operand is a 0. The S and V Flags is
cleared.
Example 4
If Register DFh contains the value ← (00000000b), Register 07h contains the value 1Fh,
and Register
1Fh contains the value BDh (10111101b) (bit 7, bit 5, bit 4, bit 3, bit 2, and
bit 0 are being tested if they are 0), the statement:
TM DFh, @07h
Op Code: 75 07 DF
sets the Z Flag indicating the tested bits in the destination operand are 0. The S is set, and
the V Flag is cleared.
Example 5
If Working Register R13 contains the value F1h (11110001b), the statement:
TM R13, #02h
Op Code: 76 ED, 02
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