MC81F4204
98 April 24, 2012 Ver.1.41
T1SCR
TIMER 1 STATUS AND CONTROL REGISTER 00B3H
To enable the timer 1 match interrupt, you must set “1” to T1MIE.
When the timer 1 match interrupt sub-routine is serviced, the timer 1 match interrupt request flag bit,
T1MIR(IRQH.5), is automatically cleared..
To enable the timer 1 overflow interrupt, you must set “1” to T1OVIE.
When the timer 1 overflow interrupt sub-routine is serviced, the timer 1 overflow interrupt request flag
bit, T1OVIR(IRQH.4), is automatically cleared.
7 6 5 4 3 2 1 0
T1SCR
–
T1MS T1CC T1CS Reset value: 00H
R/W R/W R/W R/W R/W R/W R/W R/W
–
bit7 Not used for MC81F4204
00: Interval mode (T1O)
01: PWM mode (OVF and match
interrupt can occur)
T1MS
Timer 1 Mode Selection Bit
1X: Capture mode (OVF can occur)
0: No effect
T1CC
Timer 1 Counter Clear Bit
1: Clear the Timer 1 counter (When
write, automatically cleared “0” after
being cleared counter)
0000: Counter stop
0001: Not available
0010: Not available
0011: Not available
0100: Not available
0101: External clock (EC1) rising edge
0110: External clock (EC1) falling edge
0111: Not available
1000: fxx/1
1001: fxx/2
1010: fxx/4
1011: fxx/8
1100: fxx/16
1101: fxx/64
1110: fxx/256
T1CS
Timer 1 Clock Selection Bits
1111: fxx/1024
Note :
You must set the T1CC(T1SCR.4) bit after set T1DR register. The timer 1 counter value is
compared with timer 1 buffer register instead of T1DR. And T1DR value is copied to timer 1
buffer.
To Next Page
Loading...