Chapter 6 6-7
Error Reporting
The Event-Status Register and Event-Status Register B
The Event-Status Register and Event-Status Register B
The event-status register and event-status register B are the other two registers in the
status-reporting structure (see Figure 6-1). They are selectively summarized by bits in the
status byte via enable registers. The event-status registers consist of latched bits.
A latched bit is set at the beginning of a specific trigger condition in the instrument. It can
only be cleared by reading the register. The bit will not be reactivated until the condition
occurs again. If a bit in one of these two registers is enabled, it is summarized by the
summary bit in the status byte. The registers are enabled using the commands ESE
nn
; and
ESNB
nn
;, both of which work in the same manner as SRE
nn
. The units variable nn
represents the binary equivalent of the bit in the status byte.
If a bit in one of the event-status registers is enabled, and therefore, the summary bit in
the status byte is enabled, an SRQ will be generated. The SRQ will not be cleared until one
of the five following conditions transpire:
• The event-status register is read, clearing the latched bit.
• The summary bit in the status byte is disabled.
• The event-status register bit is disabled.
• The status registers are cleared with the CLES; command.
• An instrument preset is performed.
Service requests generated when there are error messages or when the instrument is
waiting for the group execute trigger (GET) command are cleared by:
• reading the errors
• issuing GET (disabling the bits)
• clearing the status registers
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