Altera DE1-SoC - Page 37

DE1-SoC User Manual
36
www.terasic.com
March 14, 2014
The registers in the TV decoder can be accessed and set through serial I2C bus by the Cyclone V
SoC FPGA or HPS. Note that the I2C address W/R of the TV decoder (U4) is 0x40/0x41. The pin
assignment of TV decoder is listed in Table 3-17. More information about the ADV7180 is
available on the manufacturer’s website, or in the directory \DE1_SOC_datasheets\Video Decoder
of DE1-SoC System CD.
Figure 3-23 Connections between the FPGA and TV Decoder
Table 3-17 Pin Assignment of TV Decoder
Signal Name
FPGA Pin No.
Description
I/O Standard
TD_DATA [0]
PIN_D2
TV Decoder Data[0]
3.3V
TD_DATA [1]
PIN_B1
TV Decoder Data[1]
3.3V
TD_DATA [2]
PIN_E2
TV Decoder Data[2]
3.3V
TD_DATA [3]
PIN_B2
TV Decoder Data[3]
3.3V
TD_DATA [4]
PIN_D1
TV Decoder Data[4]
3.3V
TD_DATA [5]
PIN_E1
TV Decoder Data[5]
3.3V
TD_DATA [6]
PIN_C2
TV Decoder Data[6]
3.3V
TD_DATA [7]
PIN_B3
TV Decoder Data[7]
3.3V
TD_HS
PIN_A5
TV Decoder H_SYNC
3.3V
TD_VS
PIN_A3
TV Decoder V_SYNC
3.3V
TD_CLK27
PIN_H15
TV Decoder Clock Input.
3.3V
TD_RESET_N
PIN_F6
TV Decoder Reset
3.3V
I2C_SCLK
PIN_J12 or PIN_E23
I2C Clock
3.3V
I2C_SDAT
PIN_K12 or PIN_C24
I2C Data
3.3V
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