The registers in the TV decoder can be accessed and set through serial I2C bus by the Cyclone V
SoC FPGA or HPS. Note that the I2C address W/R of the TV decoder (U4) is 0x40/0x41. The pin
assignment of TV decoder is listed in Table 3-17. More information about the ADV7180 is
available on the manufacturerās website, or in the directory \DE1_SOC_datasheets\Video Decoder
of DE1-SoC System CD.
Figure 3-23 Connections between the FPGA and TV Decoder
Table 3-17 Pin Assignment of TV Decoder
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