Altera DE1-SoC - Page 42

DE1-SoC User Manual
41
www.terasic.com
March 14, 2014
Figure 3-27 Connections between the FPGA and PS/2
Figure 3-28 Y-Cable for using keyboard and mouse simultaneously
Table 3-21 Pin Assignment of PS/2
Signal Name
FPGA Pin No.
Description
I/O Standard
PS2_CLK
PIN_AD7
PS/2 Clock
3.3V
PS2_DAT
PIN_AE7
PS/2 Data
3.3V
PS2_CLK2
PIN_AD9
PS/2 Clock (reserved for second PS/2 device)
3.3V
PS2_DAT2
PIN_AE9
PS/2 Data (reserved for second PS/2 device)
3.3V
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