Altera DE1-SoC - Page 76

DE1-SoC User Manual
75
www.terasic.com
March 14, 2014
check), one stop bit (always one), and one acknowledge bit (always zero). After sending out the
parity check bit, the controller should release the data line, and the device will detect any state
change on the data line in the next clock cycle. If there’s no change on the data line for one clock
cycle, the device will pull low the data line again as an acknowledgement which means that the data
is correctly received.
After the power on cycle of the PS/2 mouse, it enters into stream mode automatically and disable
data transmit unless an enabling instruction is received. Figure 5-11 shows the waveform while
communication happening on two lines.
Figure 5-11 Waveform of clock and data signals during data transmission
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 Project directory: DE1_SoC_PS2_DEMO
 Bitstream used: DE1_SoC_PS2_DEMO.sof
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