Altera DE1-SoC - Page 78

DE1-SoC User Manual
77
www.terasic.com
March 14, 2014
Figure 5-12 Block diagram of the IR emitter LED and receiver demonstration
Figure 5-12 shows the block diagram of the design. It implements a IR TX Controller and a IR RX
Controller. When KEY0 is pressed, data test pattern generator will generate data to the IR TX
Controller continuously. When IR TX Controller is active, it will format the data to be compatible
with NEC IR transmission protocol and send it out through the IR emitter LED. The IR receiver
will decode the received data and display it on the six HEXs. Users can also use a remote to send
data to the IR Receiver. The main function of IR TX /RX controller and IR remote in this
demonstration is described in the following sections.
 IR TX Controller
Users can input 8-bit address and 8-bit command into the IR TX Controller. The IR TX Controller will
encode the address and command first before sending it out according to NEC IR transmission protocol
through the IR emitter LED. The input clock of IR TX Controller should be 50MHz.
The NEC IR transmission protocol uses pulse distance to encode the message bits. Each pulse burst is
562.5µs in length with a carrier frequency of 38kHz (26.3µs).
Figure 5-13 shows the duration of logical “1” and “0”. Logical bits are transmitted as follows:
• Logical '0' – a 562.5µs pulse burst followed by a 562.5µs space with a total transmit time
of 1.125ms
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