Altera DE1-SoC - Page 81

DE1-SoC User Manual
80
www.terasic.com
March 14, 2014
Lead Code 1bit Custom Code 16bits Key Code 8bits
Inv Key Code
8bits
End
Code
1bit
Figure 5-16 The transmitting frame of the IR remote controller
 IR RX Controller
The following demonstration shows how to implement the IP of IR receiver controller in the FPGA.
Figure 5-17 shows the modules used in this demo, including Code Detector, State Machine, and
Shift Register. At the beginning the IR receiver demodulates the signal inputs to the Code Detector .
The Code Detector will check the Lead Code and feedback the examination result to the State
Machine.
The State Machine block will change the state from IDLE to GUIDANCE once the Lead Code is
detected. If the Code Detector detects the Custom Code status, the current state will change from
GUIDANCE to DATAREAD state. The Code Detector will also save the receiving data and output
to the Shift Register and display on the 7-segment. Figure 5-18 shows the state shift diagram of
State Machine block. The input clock should be 50MHz.
Figure 5-17 Modules in the IR Receiver controller
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