Altera DE1-SoC - Page 85

DE1-SoC User Manual
84
www.terasic.com
March 14, 2014
 DE1-SoC board x1
 Trimmer Potentiometer x1
 Wire Strip x3
 Demonstration File Locations
 Hardware project directory: DE1_SoC_ADC
 Bitstream used: DE1_SoC_ADC.sof
 Software project directory: DE1_SoC_ADC software
 Demo batch file : DE1_SoC_ADC\demo_batch\ DE1_SoC_ADC.bat
 Demonstration Setup and Instructions
 Connect the trimmer to corresponding ADC channel on the 2x5 header, as shown in
Figure 5-21, as well as the +5V and GND signals. The setup shown above is
connected to ADC channel 0.
 Execute the demo batch file DE1_SoC_ADC.bat to load the bitstream and software
execution file to the FPGA.
 The Nios II console will display the voltage of the specified channel voltage result
information
Figure 5-21 Hardware setup for the ADC reading demonstration
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