Level One Memory System
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-10
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Synchronous abort exceptions
The following registers are updated when a synchronous abort exception is taken:
Fault Address Register
There are two fault address registers, one for prefetch aborts (IFAR) and one for
data aborts (DFAR). These indicate the address of the memory access that caused
the fault. See Fault Status and Address Registers on page 4-47.
Auxiliary Fault Status Register
There are two auxiliary fault status registers, one for prefetch aborts (AIFSR) and
one for data aborts (ADFSR). These record additional information about the
nature and location of the fault, including whether it was a recoverable error or
not, whether it occurred in the cache or AXI master interface, ATCM or BTCM
and, if appropriate, which cache way the error occurred in. The cache index is not
recorded on a synchronous abort, because this information can be derived from
the fault address. See Fault Status and Address Registers on page 4-47.
Asynchronous abort exceptions
The following register is updated when an asynchronous abort exception is taken:
Auxiliary Data Fault Status Register
The ADFSR is updated to indicate whether or not the fault was recoverable,
whether it occurred in the cache, ATCM or BTCM and, if appropriate, which
cache set and way the error occurred in. Because the DFAR is not updated on
asynchronous aborts, asynchronous aborts cannot normally be located, except
when the error occurred in the cache.
The effect of debug events on these registers is described in Debug exception on page 12-44.
8.3.3 Correctable Fault Location Register
Correctable faults are normally automatically corrected by the processor but, depending on the
configuration and on the access that generated the fault, an exception might not be generated,
and the fault status registers might not be updated. In all cases, information about the location
of the fault is recorded in the Correctable Fault Location Register (CFLR).
The CFLR also records information about ACP Dcache lookups that cause a correctable error.
All correctable faults are recorded in the same register, regardless of whether it was an
instruction-fetch, a data-access, an AXI slave access, that generated the fault, and whether the
fault occurred in the ATCM, BTCM or cache. The CFLR contains information to identify what
sort of access generated the fault, and which device it occurred in. See Correctable Fault
Location Register on page 4-75 for more information about the format of this register. Each time
the CFLR is updated, the information already in the CFLR is discarded and therefore the CFLR
can only contain information about the most recent correctable fault.
8.3.4 Usage models
This section describes some ways in which errors can be handled in a system. Exactly how you
program the processor to handle errors depends on the configuration of your processor and
system, and what you are trying to achieve.
If an abort exception is taken, the abort handler reads the information in the link register, SPSR,
and fault status registers to determine the type of abort. Some types of abort are fatal to the
system, and others can be fixed, and program execution resumed. For example, an MPU
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