Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-33
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12.4.19 Device Power-down and Reset Status Register
The DBGPRSR Register characteristics are:
Purpose Provides information about the reset and power-down state of the
processor.
Usage constraints The DBGPRSR Register is a read-only register, with reads of the register
also resetting some register bits.
Configurations Available in all processor configurations.
Attributes See Table 12-24 on page 12-34.
Figure 12-15 shows the DBGPRSR bit assignments.
Figure 12-15 DBGPRSR Register bit assignments
Table 12-24 on page 12-34 shows the DBGPRSR bit assignments.
[2] Hold internal
reset
Hold internal reset bit. This bit can be used to prevent the processor from running again before
the debugger detects a power-down event and restores the state of the debug registers in the
processor. This bit does not have any effect on initial system power-up as nSYSPORESET
clears it.
0 = Do not hold internal reset on power-up or warm reset. This is the reset value.
1 = Hold the processor non-debug logic in reset on warm reset until this flag is cleared.
[1] Force
internal reset
When a 1 is written to this bit, the processor asserts the DBGRSTREQ output for four cycles.
You can connect this output to an external reset controller that, in turn, resets the processor.
[0] No
power-down
When set to 1, the DBGNOPWRDWN output signal is HIGH. This output connects to the
system power controller and is interpreted as a request to operate in emulate mode. In this mode,
the processor is not actually powered down when requested by software or hardware
handshakes. This mode is useful when debugging applications on top of working operating
systems.
0 = DBGNOPWRDWN is LOW. This is the reset value
1 = DBGNOPWRDWN is HIGH.
Table 12-23 DBGPRCR Register bit assignments (continued)
Bits Name Function
31
0
3
Reserved
214
Sticky reset status
Reset status
Sticky power-down status
Power-down status
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