ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. iv
ID073015 Non-Confidential
3.6 Program status registers 3-9
3.7 Exceptions 3-14
3.8 Acceleration of execution environments 3-25
3.9 Unaligned and mixed-endian data access support 3-26
3.10 Big-endian instruction support 3-27
Chapter 4 System Control
4.1 About system control 4-2
4.2 Register summary 4-7
4.3 Register descriptions 4-9
Chapter 5 Prefetch Unit
5.1 About the prefetch unit 5-2
5.2 Branch prediction 5-3
5.3 Return stack 5-5
5.4 Controlling instruction prefetch and program flow prediction 5-6
Chapter 6 Events and Performance Monitor
6.1 About the events 6-2
6.2 About the PMU 6-6
6.3 Performance monitoring registers 6-7
6.4 Event bus interface 6-19
Chapter 7 Memory Protection Unit
7.1 About the MPU 7-2
7.2 Memory types 7-7
7.3 Region attributes 7-8
7.4 MPU interaction with memory system 7-9
7.5 MPU faults 7-10
7.6 MPU software-accessible registers 7-11
Chapter 8 Level One Memory System
8.1 About the L1 memory system 8-2
8.2 About the error detection and correction schemes 8-4
8.3 Fault handling 8-7
8.4 About the TCMs 8-13
8.5 About the caches 8-18
8.6 Internal exclusive monitor 8-34
8.7 Memory types and L1 memory system behavior 8-35
8.8 Error detection events 8-36
Chapter 9 Level Two Interface
9.1 About the L2 interface 9-2
9.2 AXI master interface 9-3
9.3 AXI master interface transfers 9-7
9.4 AXI slave interface 9-20
9.5 Enabling or disabling AXI slave accesses 9-23
9.6 Accessing RAMs using the AXI slave interface 9-24
Chapter 10 Power Control
10.1 About power control 10-2
10.2 Power management 10-3
Chapter 11 FPU Programmers Model
11.1 About the FPU programmers model 11-2
11.2 General-purpose registers 11-3
11.3 System registers 11-4
11.4 Modes of operation 11-11
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