ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. v
ID073015 Non-Confidential
11.5 Compliance with the IEEE 754 standard 11-12
Chapter 12 Debug
12.1 Debug systems 12-2
12.2 About the debug unit 12-3
12.3 Debug register interface 12-5
12.4 Debug register descriptions 12-10
12.5 Management registers 12-35
12.6 Debug events 12-42
12.7 Debug exception 12-44
12.8 Debug state 12-47
12.9 Cache debug 12-53
12.10 External debug interface 12-54
12.11 Using the debug functionality 12-57
12.12 Debugging systems with energy management capabilities 12-74
Chapter 13 Integration Test Registers
13.1 About Integration Test Registers 13-2
13.2 Summary of the processor registers used for integration testing 13-3
13.3 Processor integration testing 13-4
Appendix A Signal Descriptions
A.1 About the processor signal descriptions A-2
A.2 Global signals A-3
A.3 Configuration signals A-4
A.4 Interrupt signals, including VIC interface signals A-7
A.5 L2 interface signals A-8
A.6 TCM interface signals A-13
A.7 Redundant processor signals A-16
A.8 Debug interface signals A-17
A.9 ETM interface signals A-19
A.10 Test signals A-20
A.11 MBIST signals A-21
A.12 Validation signals A-22
A.13 FPU signals A-23
Appendix B AC Characteristics
B.1 Processor timing B-2
B.2 Processor timing parameters B-3
Appendix C Cycle Timings and Interlock Behavior
C.1 About cycle timings and interlock behavior C-3
C.2 Register interlock examples C-6
C.3 Data processing instructions C-7
C.4 QADD, QDADD, QSUB, and QDSUB instructions C-9
C.5 Media data-processing C-10
C.6 Sum of Absolute Differences (SAD) C-11
C.7 Multiplies C-12
C.8 Divide C-14
C.9 Branches C-15
C.10 Processor state updating instructions C-16
C.11 Single load and store instructions C-17
C.12 Load and Store Double instructions C-20
C.13 Load and Store Multiple instructions C-21
C.14 RFE and SRS instructions C-24
C.15 Synchronization instructions C-25
C.16 Coprocessor instructions C-26
C.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions C-27
C.18 Miscellaneous instructions C-28
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