Preface
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ix
ID073015 Non-Confidential
Chapter 8 Level One Memory System
Read this for a description of the Level One (L1) memory system.
Chapter 9 Level Two Interface
Read this for a description of the features of the Level Two (L2) interface not
covered in the AMBA
®
AXI Protocol Specification.
Chapter 10 Power Control
Read this for a description of the power control facilities.
Chapter 11 FPU Programmers Model
Read this for a description of the Floating Point Unit (FPU) support in the
Cortex-R4F processor.
Chapter 12 Debug
Read this for a description of the debug support.
Chapter 13 Integration Test Registers
Read this for a description of the Integration Test Registers, and of integration
testing of the processor with an ETM-R4 trace macrocell.
Appendix A Signal Descriptions
Read this for a description of the inputs and outputs of the processor.
Appendix B AC Characteristics
Read this for a description of the timing parameters applicable to the processor.
Appendix C Cycle Timings and Interlock Behavior
Read this for a description of the instruction cycle timing and instruction
interlocks.
Appendix D ECC Schemes
Read this for a description of how to select the Error Checking and Correction
(ECC) scheme depending on the Tightly-Coupled Memory (TCM) configuration.
Appendix E Revisions
Read this for a description of the technical changes between released issues of this
book.
Conventions
Conventions that this book can use are described in:
• Typographical
• Timing diagrams on page x
• Signals on page x.
Typographical
The typographical conventions are:
italic Introduces special terminology, denotes cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.
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