Progressive Scan CCD Sensor
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Vert.
Shift
Reg.
Pixels Pixels Pixels Pixels
Horizontal
Shift Register
ADC VGC
Fig. 25: CCD Sensor Architecture - Progressive Scan Sensors
Sensor
ADC
FPGA
Controller
Image
Buffer
Image
Data
Image
Data
I/O
Frame Burst Start Trigger Signal
or Frame Start Trigger Signal or
Frame Counter Reset Signal or
Trigger InputCounter Reset Signal
Frame Burst Trigger Wait Signal or
Frame Trigger Wait Signal or
Exposure Active Signal or
Timer 1 Signal
Image and
Control Data
and
Power
PC
Image
and
Control
Data
VGC
Control: ROI
Fig. 26: Camera Block Diagram
Control: Gain, Black Level