16 (55) BRUKER BIOSPIN Technical Manual Version 001
Product Status and Modifications
LVDS Configuration
Firmware
The firmware is loaded via PCI and Ethernet from the TopSpin PC as part of Top-
Spin. The DPP1 driver is a part of the “diskless” LINUX.
Modification History 4.3
Table 4.2. LVDS Identification Lines H12513F1 48 Bit Interface
Signal
LVDS
Input
LVDS
Output
Resistor
Location
Comment
CHANNEL_DETECT_1 20 Not used RB48 CHANNEL_DETECT = 00 G_CNTRL
recognize connection to DPP
CHANNEL_DETECT_0 7 Not used RB52
USB pwr 19 19
These signals are connected between
the input and output LVDS connector.
USB gnd 8 8
USB + 1 1
USB - 14 14
Table 4.3. DPP1, H12513F1 Modification History
EC
Number
Date
Layout
Number
Description
Serial
Number
EC Level
3461 21.9.06 H4P2820B Introduction of the DPP1 for IPSO with
48 bit LVDS and external generation
of NV clock.
0032 not
shipped
00
3462 21.9.06 Removed the selection of NV clock
input by a placement of a resistor. Due
to a new termination, both inputs
(coax connector for 19“ and PCI pin
for AQS) are ready to operate.
< 0041
not
shipped
01
3463 21.9.06 H4P2820C Removed the modifications from lay-
out H4P2820B.
0100 02
3623 28.04.08 Corrected echo position jittering dur-
ing imaging echo experiments.
0251 03
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