Bruker DPP1 - Configuration of Interrupts; Interrupts from Logic or DSP to Host; Table 5.23: DSP Enable Register; Table 5.24: Allocation of DSP Interrupts

Description
Technical Manual Version 001 BRUKER BIOSPIN 35 (55)
Configuration of Interrupts 5.4.9
Interrupts to the DSP can be released by the internal events of the DPP logic Next
value, delayed gradient flag (GFD) and calculation time-out, or by setting the cor
-
responding bit in the mailbox register via the PCI bus and PCI controller (PLX).
Refer to the SPRU 190D technical manual, chapter 17.4.1, for more information.
Interrupts from Logic or DSP to Host
Interrupts to the host can be released by the DSP host port interrupt (HINT to
LINT1 of the PCI controller) or by setting the corresponding bit in the Mailbox Re
-
gister (to LINT2 of the PCI controller) via the EMIF Bus. Both interrupts can only
be initiated by the DSP.
The PCI controller interrupt inputs LINT1 and LINT2 are routed to the PCI connec-
tor pin INT A.
The PLX controller interrupt inputs are routed to the PCI bus INT A.
Table 5.23: DSP Enable Register
DSP Register Name Address Value Function
GPEN 01B0 0000 0xF0 No GPIO pin
GPPOL 01B0 0024 0x40 Polarity
Table 5.24: Allocation of DSP Interrupts
DSP Interrupt Input Source Signal Function Active Level
INT 4 INT INT High
INT 5 GFD GFD High
INT 6 IWR_DSP Logic to DSP:
„Read Pipeline Register“
High
INT 7 CNT_ERR Calculation error counter
> time-out value
High