Bruker DPP1 - Tables

Technical Manual Version 001 BRUKER BIOSPIN 53 (55)
Tables
1 Introduction 5
2 Installation and Handling 9
3 Reference Numbers 13
Table 3.1. Parts and Assemblies for the DPP1, H12513F1 ................................... 13
Table 3.2. Accessories ........................................................................................ 13
4 Product Status and Modifications 15
Table 4.1. PCI Interrupt Selection ........................................................................ 15
Table 4.2. LVDS Identification Lines H12513F1 48 Bit Interface ........................... 16
Table 4.3. DPP1, H12513F1 Modification History ................................................. 16
5 Description 17
Table 5.1: Word on the LVDS 48 bit 80 MHz Parallel Interface ............................. 20
Table 5.2: Bit Fields of the DPP Input and Output Word ....................................... 20
Table 5.3: PCI Local Bus Addresses .................................................................... 23
Table 5.4: Local Bus Chip Select Signals Usage .................................................. 24
Table 5.5: Local Bus Chip Select Registers .......................................................... 24
Table 5.6: Local Bus Configuration Registers ....................................................... 24
Table 5.7: Local Bus Control Registers ................................................................ 26
Table 5.8: Local Bus Address Map ....................................................................... 26
Table 5.9: Type of Flash Proms used on the DPP ................................................ 27
Table 5.10: DSP HPI Register ............................................................................... 27
Table 5.11: DSP HPI Control Register Host View ................................................... 27
Table 5.12: DSP HPI Control Register CPU View ................................................... 28
Table 5.13: DPP Pipeline Register ......................................................................... 28
Table 5.14: Field Description of the Mailbox Register ............................................. 28
Table 5.15: Local Bus Memory Regions ................................................................. 29
Table 5.16: DSP Configuration Pins ....................................................................... 29
Table 5.17: DSP Address Map ............................................................................... 30
Table 5.18: EMIF Control Register ......................................................................... 32
Table 5.19: Bit Description of EMIF Space CE Control Register ............................. 32
Table 5.20: EMIF Space Control Register Field Description ................................... 33
Table 5.21: EMIF CE Space Control Register Field Description .............................. 33
Table 5.22: PLL Register Contents ........................................................................ 34
Table 5.23: DSP Enable Register .......................................................................... 35
Table 5.24: Allocation of DSP Interrupts ................................................................ 35
Table 5.25: PLX Controller Interrupts ..................................................................... 36
Table 5.26: Configuration Register and Resulting Memory Allocation ..................... 36
Table 5.27: Bit Fields of the Space Control Register .............................................. 37
Table 5.28: Bit Field Description ............................................................................ 37