Bruker DPP1 - DSP Boot Mode and Configuration; DSP Reset; Local Address Layout; Local Bus Chip Select Usage

Description
Technical Manual Version 001 BRUKER BIOSPIN 29 (55)
DSP Reset
The DSP is reset by writing any data on address zero in the local region 2 of the
PCI smart target accelerator. The reset has no effect on the control logic.
Local Address Layout 5.4.7
Local Bus Chip Select Usage
The DSP 6713 5.4.8
DSP Boot Mode and Configuration
The C6713 uses a variety of boot configurations to determine what actions the de-
vice is to perform after reset for proper device initialization.
The table below describes the device configuration pins, which are set up via in-
ternal or external pull-up/pull-down resistors through the HPI data pins, and
CLKMODE0 pin. These pins must be in a desired state until reset is released.
0000 0000 CS2 DSP Reset W xxxx
Table 5.15: Local Bus Memory Regions
PLX Select Signal DSP Memory Allocation Module
PLX CS 0 DSP HPI
PLX CS 1 DSP CE1 Pipeline Register
PLX CS 2 DSP Reset
PLX CS 3 FLash Memory
Table 5.16: DSP Configuration Pins
Configuration
Pin
Connect to Description
HD 12
1
EMIF Big Endian mode correctness [C6713B]
0 – The EMIF data will always be presented on the ED (7:0) side of the
bus, regardless of the Endianess mode (Little / Big Endian).
1 – In Little Endian mode (HD8 = 1), the 8 bit or 16 bit EMIF data will be
present on the ED (7:0) side of the bus.
In Big Endian mode (HD8 = 0), the 8 bit or 16 bit EMIF data will be pres-
ent on the ED (31:24) side of the bus [default].