Bruker DPP1 - Features; Fifos; Lvds; Memory

Description
Technical Manual Version 001 BRUKER BIOSPIN 19 (55)
LVDS
The data from the GCNTR to the DPP1 and from the DPP1 to the gradient ampli-
fier is transmitted via two serial LVDS links. The word width transmitted is 48 bit
and the word transfer speed is 80 MHz.
FIFO’s
Each LVDS connection is connected to an input and output FIFO. The organiza-
tion of the synchronous FIFO is 8192 x 36 bit.
Memory
The external synchronous SRAM on the EMIF bus of the DSP is 128 KB x 36 bit.
Operation
The Digital Preemphasis Processor (DPP) transmits new gradient data in a pre-
defined time pattern to the gradient amplifier. In each time slot the software tests if
a new data package is transferred from the GCU. The DSP reads the new data
and uses it for the next calculation. If no new data set is available the output data
to the gradient amplifier is calculated with a function of the old output data.
Features
• Floating point DSP TMS320C6713 with internal:
- Level 1 program cache (L1P) 4 KB.
- Level 1 data cache (L1D) 4 KB.
- Level 2 memory cache consists of 256 KB memory space that is shared
between data and memory space.
• 128 KB x 36 bit expansion SRAM.
• PCI SMART Target I/O controller PCI9030, 5 V I/O tolerant.
• 48 bit LVDS interface 80 MHz.
• Input/Output FIFO 8 KB x 36 bit.
• “Next Value” clock cycle is software programmable from 100 ns up to 1,023
sec.
LVDS Data Structure 5.3
The structure of the 48 bit word is identical at the receiver and transmitter.