Bruker DPP1 - Table 5.18: EMIF Control Register; Table 5.19: Bit Description of EMIF Space CE Control Register; The DSP External Memory Interface (EMIF)

32 (55) BRUKER BIOSPIN Technical Manual Version 001
Description
The DSP External Memory Interface (EMIF)
The DSP EMIF support a glue-less interface to a variety of external devices, in-
cluding:
• Pipe lined synchronous burst SRAM (SBSRAM).
• Synchronous DRAM (SDRAM).
• Asynchronous devices, including SRAM, ROM and FIFO’s.
If multiple requests arrive simultaneously, the EMIF prioritizes them and performs
the necessary number of operations. The behavior of the EMIF is defined in dedi
-
cated registers.
Table 5.18: EMIF Control Register
Register Name Address Value Comment
Global Control reg. 0 x 180 0000 0 x 0000 30F8
Space control reg. CE 0 0 x 180 0008 0 x FFFF FF43 32 bit SBRAM
Space control reg. CE 1 0 x 180 0004 0 x 1221 C222
0 x 1091 4221 possible
32 bit asyn. RAM
Space control reg. CE 2 0 x 180 0010 0 x FFFF FF43 32 bit SBRAM
Space control reg. CE 3 0 x 180 0014 0 x FFFF FF43 32 bit SBRAM
Table 5.19: Bit Description of EMIF Space CE Control Register
Bit 31..28 Bit 27..22 Bit 21..20 Bit 19..16
Write setup Write strobe Write hold Read setup
RW, +1111 RW, +111111 RW,+ 11 RW, + 1111
Bit15..14 Bit 13..8 Bit 7..4 Bit 3 Bit 2..0
TA Read strobe MTYPE Write hold MSB(1) Read hold
RW, +1111 RW, +111111 RW,+ 11 RW, + 0 RW, + 011