Description
Technical Manual Version 001 BRUKER BIOSPIN 43 (55)
After initializing the LVDS transmitter it is necessary to reset the input FIFO of the
receiving unit.
Format of the Information Register
Format of the ADR Debug Register
Table 5.39: Information Register Bit Fields
Bits
10..6 5 4..0
Fields
PR6 Version NV Lock NV Register
Table 5.40: Information Register Bit Field Description
Field Value Description
NV Lock
0
1
Default is 1.
Locked. The phase of the NV clock is shifted to the edge of the LVDS clock.
Unlocked.
Table 5.41: ADR Debug Register Bit Fields
Bits
10..1 0
Fields
Fixed value NG_SM_ERR
Res
11 0000 0000 0
Table 5.42: ADR Debug Register Bit Field Description
Field Value Description
NG_SM_ERR 0
1
The phase acquisition NV clock to the LVDS clock is correct.
The LV clock edge was not correctly determined.
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