46 (55) BRUKER BIOSPIN Technical Manual Version 001
Description
• The number of transferred Next Gradient must be the same or smaller than the
number of transferred gradient packets.
• The hardware can suppress a Next Gradient and supply an appropriate error
interrupt only when the FIFO contains at least one complete gradient packet.
Serial Gradient Cycle, Serial Processing by the DSP
Figure 5.6: Gradient Cycle without Parallel Processor
Figure 5.6: Gradient cycle without parallel processor, „g
i
“ is transferred with maxi-
mum delay in a packet with „g
i+1
“ with a maximum delay to the Next Gradient.