Bruker DPP1 - Flash Prom at the Local Bus; Local Bus Address Map; Table 5.7: Local Bus Control Registers; Table 5.8: Local Bus Address Map

26 (55) BRUKER BIOSPIN Technical Manual Version 001
Description
Local Bus Address Map 5.4.4
Flash Prom at the Local Bus 5.4.5
Bus characteristics for accessing Flash PROM‘s:
Bus width: Two byte, data bit 7...0 attached; data bit 15...8 not used; there-
fore the flash prom occupies the double address area.
Cycle Control: Clock controlled.
Cycle Length: Approximately 85 nanoseconds for posting and 270 nanosec-
onds for the reading cycle.
Table 5.7: Local Bus Control Registers
PCI Addr.
Offset
Register Description Register Name
Register
Values
4C Interrupt Control / Status INTCSR 0030 0048 h
50 h PCI Target Response, Serial EE-PROM,
Initialization Control
CNTRL 1078 0000 h
54 h General Purpose I/O Control GPIOC 0024 EB40 h
70 h Hidden 1 Power Management Data Select PMDATA 0 h
74 h Hidden 2 Power Management Data Scale PMCSR[14:13] hidden,
PMCSR[7:0] used
0 h
Table 5.8: Local Bus Address Map
Acronyms
Local
Address
Space Function Mode R/W Bit
0000 CS0 DSP HPI Control Register low word R/W 15–0
0002 CS0 DSP HPI Control Register high word R/W 15–0
0004 CS0 DSP HPI Address Register low word R/W 15–0
0006 CS0 DSP HPI Address Register high word R/W 15–0
0008 CS0 DSP HPI Data Register low word R/W 15–0
000A CS0 DSP HPI Data Register high word R/W 15–0
0000 CS1 Pipeline Register W 31–0
0000 CS2 DSP Reset W xxxx
0000 – FF CS3 Flash Memory W/R 15–0