7.2.43.4 Sub-Register 0x2A:08 – TC_PG_CTRL
Transmitter Calibration – Pulse Generator Control
Register file: 0x2A – Transmitter Calibration block, sub-register 0x08, is a 16-bit control register that contains
the following bitmapped sub-fields:
REG:2A:08 – TC_PG_CTRL – Transmitter Calibration – Pulse Generator Control Settings
Definition of the bit fields within Sub-Register 0x2A:08 -TC_PG_CTRL:
Description of fields within Sub-Register -TC_PG_CTRL Sub-Register 0x28:0C–
RF_TXCTRL
Start the pulse generator calibration. Note: This bit is self clearing.
PG_TMEAS
reg:2A:08 bit5:2
Number of clock cycles over which to run the pulse generator cal counter. These
are the upper 4 MSb's of a 10 bit counter clocked by the system clock.
This register controls the pulse generator calibration. When a calibration is complete, it generates a pulse
generator delay count based on the current TC_PGDELAY value. The count value is then stored automatically
into the TC_PG_STATUS register. This delay count gives a consistent reflection of the bandwidth regardless
of temperature.
7.2.43.5 Sub-Register 0x2A:09 – TC_PG_STATUS
Transmitter Calibration – PG Status
Register file: 0x2A – Transmitter Calibration block, sub-register 0x09, is a 32 bit status register that contains
the following bitmapped sub-fields:
REG:2A:09 – TC_PG_STATUS – Transmitter Calibration – Pulse Generator Status
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