Description of fields within Register file: 0x04 – System Configuration
Receiver Mode 110 kbps data rate. This configuration when set to 1 will cause the receiver
to look for long SFD and process the PHY Header and RX data as per the 110 kbps frame
mode. When this configuration is 0, (the default), the receiver will look for short SFD and
will determine the RX data rate from the PHY header as either 850 kbps or 6.8 Mbps.
These bits are reserved and should always be set to zero to avoid any malfunction of the
device.
Receive Wait Timeout Enable. When set RX Enable will initialise an RX_FWTO down count
which will disable the receiver if no valid frame is received before the timeout occurs. The
timeout period is set in Register file: 0x0C – Receive Frame Wait Timeout Period. The
occurrence of the timeout is signalled by the RXRFTO event status bit in Register file: 0x0F –
System Event Status Register.
Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically.
Its operation changes depending on whether the IC is operating in single or double buffered
modes. The default value is 0. With this setting, the IC will not automatically re-enable the
receiver but will stop receiving and return to idle mode whenever any receive events
happen. This includes receiving a frame but also failing to receive a frame because of some
error condition, for example an error in the PHY header (as reported by the RXPHE event
status bit in Register file: 0x0F – System Event Status Register). In such cases if the host
wants to re-enable the receiver it must do it explicitly, using the RXENAB bit in Register file:
0x0D – System Control Register. The operation when RXAUTR = 1 is as follows:
(a) Double-buffered mode: After a frame reception event or failure (except a frame
wait timeout), the receiver will re-enable to receive another frame.
(b) Single-buffered mode: After a frame reception failure (except a frame wait
timeout), the receiver will re-enable to re-attempt reception.
For more information on frame reception see section 4 – Message Reception.
Note: In double-buffered mode when automatic frame acknowledgement is enabled (by
the AUTOACK bit below) the receiver will be re-enabled after the ACK frame has been
transmitted.
Automatic Acknowledgement Enable. Default value 0. This is the enable for the Automatic
Acknowledgement function. See section 5.3– Automatic Acknowledgement for details of
operation of Automatic Acknowledgement.
AACKPEND
reg:04:00
bit:31
Automatic Acknowledgement Pending bit control. Default value 0. The value of the
AACKPEND bit is copied into the Frame Pending bit in the Frame Control field of the
DW1000 automatically generated ACK frame. See section 5.2 – Frame filtering for details of
operation of frame filtering.
7.2.7 Register file: 0x05 – Reserved
Reserved – this register file is reserved
Register map register file 0x05 is reserved for future use. Please take care not to write to this register as
doing so may cause the DW1000 to malfunction.
To Next Page
Loading...