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EIP 545A - Page 52

EIP 545A
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SIGN1 FlCANT ADDRESSES,
1/0
PORTS
If an
I10
bit
is
configured as an output, the number read by test 10 will be the same number that
is
pro-
grammed. If an
I10
bit
is
configured
as
an input, the number read by test 10 will be the input signal level
on the
I10 line. Therefore, if an
I10
port
is
programmed, and then read, the number displayed may not
correspond to the number programmed because some bits of the
I10
port may be configured as inputs.
Figure 6-7.
110
Addresses.
DESCRIPTION
PIA on Count Chain (A1061
PIA on Gate Generator (A1071
Frequency Control PIA on Converter
Control A108
Programmable Counter PIA on
Converter Control (A1
08)
PIA on Band 2 Converter (A1091
PIA on Front Panel Logic (A1 11)
PIA on BCDIRemote (A1021
PIA on DAC Board (A1031
ADDRESS OF
PA PORTS
ACOO
9900
9840
9820
9880
9808
9A00
A820
ADDRESS OF
PB PORTS
AC02
9902
9842
9822
9882
980A
9A02
A822
DESCRIPTION
GPlB Address Switch
ADDRESS
9C04
Scans by ArtekMedia © 2007

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