Chapter 2. API Reference
For interrupt transactions, the CPU can switch to other tasks when a transaction is in progress. This saves the CPU
time but increases the transaction duration. See Interrupt Transactions. For polling transactions, it does not block
the task but allows to do polling when the transaction is in progress. For more information, see Polling Transactions.
If DMA is enabled, setting up the linked list requires about 2 us per transaction. When a master is transferring data,
it automatically reads the data from the linked list. If DMA is not enabled, the CPU has to write and read each byte
from the FIFO by itself. Usually, this is faster than 2 us, but the transaction length is limited to 64 bytes for both
write and read.
Typical transaction duration for one byte of data are given below.
• Interrupt Transaction via DMA: 23 µs.
• Interrupt Transaction via CPU: 22 µs.
• Polling Transaction via DMA: 9 µs.
• Polling Transaction via CPU: 8 µs.
SPI Clock Frequency Transferring each byte takes eight times the clock period 8/fspi.
Cache Miss The default config puts only the ISR into the IRAM. Other SPI related functions, including the driver
itself and the callback, might suffer from cache misses and will need to wait until the code is read from flash. Select
CONFIG_SPI_MASTER_IN_IRAM to put the whole SPI driver into IRAM and put the entire callback(s) and its callee
functions into IRAM to prevent cache misses.
For an interrupt transaction, the overall cost is 20+8n/Fspi[MHz] [us] for n bytes transferred in one transaction.
Hence, the transferring speed is: n/(20+8n/Fspi). An example of transferring speed at 8 MHz clock speed is given
in the following table.
Frequency
(MHz)
Transaction Interval
(us)
Transaction Length
(bytes)
Total Time
(us)
Total Speed
(KBps)
8 25 1 26 38.5
8 25 8 33 242.4
8 25 16 41 490.2
8 25 64 89 719.1
8 25 128 153 836.6
When a transaction length is short, the cost of transaction interval is high. If possible, try to squash several short
transactions into one transaction to achieve a higher transfer speed.
Please note that the ISR is disabled during flash operation by default. To keep sending transactions during
flash operations, enable CONFIG_SPI_MASTER_ISR_IN_IRAM and set ESP_INTR_FLAG_IRAM in the member
spi_bus_config_t::intr_flags. In this case, all the transactions queued before starting flash operations
will be handled by the ISR in parallel. Also note that the callback of each Device and their callee functions should
be in IRAM, or your callback will crash due to cache miss. For more details, see IRAM-Safe Interrupt Handlers.
Application Example
The code example for using the SPI master half duplex mode to read/write a AT93C46D EEPROM (8-bit mode)
can be found in the peripherals/spi_master/hd_eeprom directory of ESP-IDF examples.
API Reference - SPI Common
Header File
• components/hal/include/hal/spi_types.h
Espressif Systems 370
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