5700MSC-IP
IP Network Grand Master Clock & Video Master Clock System
Page - 30 Revision 0.2
Figure 3-6 shows the timing relationship between the outputs of the 5700MSC-IP and the applied
NTSC video reference. The master oscillator will lock its frequency to the NTSC video reference, and
all outputs will become frequency locked. This frequency locking process uses both the horizontal sync
and the colorburst to obtain an accurate lock. The applied NTSC reference should have no video
content and a low Subcarrier to Horizontal (SCH) offset to assure proper lock. The approximate SCH
value is shown in the Inputs status screen. If the SCH error is higher than 30º, the 5700MSC-IP will fall
back to locking to the horizontal edge of the video only. If the SCH error is in excess of 50º, or the
colorburst cannot be accurately measured, the 5700MSC-IP will report that the applied reference is
unlockable.
It is important to ensure that the incoming black burst reference is of good quality.
There should be no video content on the reference otherwise reference lock could be
lost, or higher jitter may be produced on the outputs.
The color frame sequence of the NTSC reference is decoded and used to phase the outputs. Because
the NTSC color frame sequence is only 2 frames long, this is not enough phase information to
deterministically lock signals which align to NTSC on longer periods. This includes 23.98Hz standards,
DARS/AES signals, and the 6/1.001Hz pulse. These signals align with NTSC once every 5 frames.
This is illustrated in Figure 3-4. The phase of these signals will be set arbitrarily and cannot be
guaranteed to be the same between different units that are locked to the same reference. The phase
may also change if the unit is restarted.
The phase locking ability of the 5700MSC-IP when supplied with an NTSC reference is summarized at
the bottom of the lock diagram (Figure 3-6). The HD standards listed apply to both the HD test
generators and the tri-level sync outputs. The serial digital video test generator outputs are phased
according to SMPTE compliant timing, which may differ from the timing shown on Tektronix
equipment.
If the NTSC reference is lost, the unit will freerun on the selected oscillator. Note than when the
Genlock Range is set to Wide, the freerun drift upon loss of reference will be much higher. When the
NTSC reference is re-applied the Lock Type menu selection controls how the 5700MSC-IP will
respond to re-align its internal oscillator with the reference.
When locked to NTSC without a ten-field reference, the AES/DARS outputs cannot be
deterministically phased. The AES/DARS/WC lck menu item located in the AES Audio menu off the
OUTPUT root menu should be set to NTSC/fractional, however the phase relationship will be chosen
arbitrarily and may change if the reference is lost or the unit is restarted.
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