evertz 5700MSC-IP - Page 8

5700MSC-IP
IP Network Grand Master Clock & Video Master Clock System
Page - iv Revision 0.2
Figures
Figure 1-1: Front View of the 5700MSC-IP .................................................................................... 1
Figure 1-2: Ethernet Port Configuration ......................................................................................... 4
Figure 1-3: PTP All Ports Menu ..................................................................................................... 7
Figure 1-4: PTP GigE 1 .................................................................................................................. 7
Figure 1-5: PCR GigE 1 Menu ....................................................................................................... 8
Figure 1-6: 5700MSC-IP Rear Panel View ..................................................................................... 9
Figure 3-1: IRIG-B127 Format and Alignment to IRIG1 Datum Pulse ........................................... 22
Figure 3-2: 29.97Hz LTC Format and Alignment to NTSC Video ................................................. 22
Figure 3-3: PAL Alignment to 1Hz Pulse and PAL Color Frame Pulse ......................................... 23
Figure 3-4: NTSC Alignment to 1/1.001Hz Pulse and 6/1.001Hz Pulse with VITC Color Framing 23
Figure 3-5: Main Oscillator Circuit Block Diagram ........................................................................ 24
Figure 3-6: Lock Diagram #1 - NTSC Reference without 10field Reference ................................. 29
Figure 3-7: Lock Diagram #2 – NTSC Reference with Ten-field Reference .................................. 31
Figure 3-8: SMPTE ST 318 Ten-field Reference on NTSC line 15 ............................................... 32
Figure 3-9: Lock Diagram #3 – PAL Genlock ............................................................................... 33
Figure 3-10: Lock Diagram #4 – HD Tri-Level Genlock Operation ............................................... 35
Figure 3-11: Lock Diagram #5 – 10MHz and Internal Frequency References .............................. 37
Figure 3-12: Lock Diagram #6 – GNSS Frequency Reference ..................................................... 39
Figure 3-13: 5700MSC-IP Jam Modes ......................................................................................... 41
Figure 3-14: 5700MSC-IP Time Reference Sources .................................................................... 43
Figure 3-15: Detail of 29.97Hz LTC Waveform Alignment to NTSC Video ................................... 45
Figure 3-16: Dropframe Timecode with Respect to Real-time over a 1-Hour Period .................... 47
Figure 3-17: Dropframe Timecode with Respect to Real-time over a 24-Hour Period .................. 47
Figure 3-18: Daily Time Jam Event for 29.97Hz Dropframe Timecode ......................................... 48
Figure 3-19: Dropframe Timecode with Respect to Real-time over One Week ............................ 49
Figure 3-20: Detail of IRIG Alignment to IRIG Datum Pulse ......................................................... 50
Figure 3-21: IRIG Input and Output Connections ......................................................................... 51
Figure 3-22: Testing the NTP Server ........................................................................................... 52
Figure 4-1: 5700MSC-IP Rear Panel ........................................................................................... 57
Figure 4-2: Pole Mounting the Smart Antenna ............................................................................. 64
Figure 5-1: Model 5700MSC-IP Front Panel Layout ..................................................................... 67
Figure 5-2: Video Sync Phase Alignment in 59.94Hz Field Rate Systems ................................... 86
Figure 5-3: Video Sync Phase Alignment in 50Hz Field Rate Systems ........................................ 86