5520A
Operators Manual
5-42
Convert the contents of variables A and B into binary, and you can read the status of the
registers. For example if A is 32, its binary equivalent is: 00000000 00100000.
Therefore, bit 5 (CME) in the ESR is set (1) and the rest of the bits are reset (0). This
means that the Calibrator tried to execute an incorrectly formed command.
By setting the bits in the ESE, you can mask (disable) the associated bits in the ESR. For
example, to prevent the occurrence of a command error from causing bit 5 (ESB) in the
serial poll status byte to go to 1, you can reset (to 0) bit 5 in the ESE register. The
following sample program accomplishes this by checking the status of the CME bit, then
toggling it if it is 1.
10 ! THIS PROGRAM RESETS BIT 5 (CME) IN THE ESE
20 PRINT @6,”*ESE 33” ! INITIAL ESE IS CME + OPC
30 GOSUB 100 ! GET AND PRINT INITIAL ESE
40 IF (A% AND 32%) THEN A% = A% - 32% ! CLEAR CME (BIT 5)
50 PRINT @6, “*ESE “;A% ! LOAD ESE WITH NEW VALUE
60 GOSUB 100 ! GET AND PRINT NEW ESE
70 END
100 PRINT @6, “*ESE?” ! ASK FOR ESE CONTENTS
110 INPUT @6, A% ! RETRIEVE REGISTER CONTENTS
120 PRINT “ESE = “;A%
130 RETURN
5-51. Instrument Status Register (ISR)
The Instrument Status Register (ISR) instrument status register (ISR)ISR (instrument
status register)gives the controller access to the state of the Calibrator, including some of
the information presented to the operator on the Control Display and the display
annunciators during local operation.
5-52. Instrument Status Change Registers
There are two registers dedicated to monitoring changes in the ISR. These are the ISCR0
(Instrument Status 1-0 Change Register) instrument status change registers (ISCR0 and
1)ISCR0, ISCR1 (instrument status change registers)and the ISCR1 (Instrument Status
0-1 Change Register). Each status change register has an associated mask register. Each
ISCR is cleared (set to 0) when the Calibrator is turned on, every time it is read, and at
each *CLS (Clear Status) command.
5-53. Instrument Status Change Enable Registers
The Instrument Status Change Enable registers (ISCE0 and ISCE1) are instrument status
change enable registers (ISCRE and 1)ISCE0, ISCE1 (instrument status change enable
registers)mask registers for the ISCR0 and ISCR1 registers. If a bit in the ISCE is
enabled (set to 1) and the corresponding bit in the ISCR makes the appropriate transition,
the ISCB bit in the Status Byte is set to 1. If all bits in the ISCE are disabled (set to 0),
the ISCB bit in the Status Byte never goes to 1. The contents of the ISCE registers are set
to 0 at power-up.
5-54. Bit Assignments for the ISR, ISCR, and ISCE
The bits in the Instrument Status, Instrument Status Change, and Instrument Status
Change Enable registers are assigned as shown in Figure 5-11.
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