TROUBLESHOOTING AND REPAIR
FREQUENCY SYNTHESIS
SINGLE-SIDEBAND MIXER
The 160- to 320-MHz from the VCO via J7 is filtered (C140-2, L70-1), attenuated
(R69-71), amplified (U50), attenuated again (R101-3, R106), and amplified (U51) and
connected to a quadrature (90-degree phase difference) 3-dB coupler (U52).
This signal, and two other audio quadrature signals from U59 are summed in the
double-balanced mixers U53 and U54 to produce two double-sideband suppressed-
carrier signals. Because of the phase relationship of the outputs of the mixers, the
summing of the two composite signals in resistor network (R75 and R76) results in the
upper-sideband component being suppressed. The predominate remaining signal is the
lower-sideband signal.
The lower-sideband signal, spanning 160 to 320 MHz in 10-kHz steps, is amplified by
U55 and applied to the N-divider where it is divided down to 1 MHz.
N-DIVIDER
The main components of the N-Divider are: triple-modulus prescaler (divide by
16/17118) U56, U57, and U58, and the N-Divider Custom Gate Array U62.
The triple-modulus prescaler (see Figure 6C-3), consists of a divide by 8/9 U58,
divide-by-2 U57A, synchronizing flip-flop U57B, and quad NOR gates U56. If all the
inputs (El, E2, E3, E4, and E5) to 8/9 divider are low, the prescaler divides by 9, and
the total division to the output (U58 pin 7, TP33) is 18.
If inputs E1 and E3 are low, the modulus of the 8 / 9 divider is controlled by the output
of the divide-by-2 U57 A. Consequently, the prescaler divides by 8 half the time and by
9 the other half, resulting in a divide by 17. U57B synchronizes the changing of the
modulus with the clocking of the subsequent stages. The N-divider gate array is
clocked by the composite prescaler output U18A via the ECL-to-TTL converter
contained in U58.
The N-divider gate array (Figure 6C-4) contains two 5-bit binary counters (A and N), a
BCD two-decade rate multiplier, and latches to interface to the controller. The
operation of the N and A counters is described in the following paragraphs.
At the beginning of a count cycle, a number is loaded into the A and N counters. The A
counter is not at its terminal count, so the output is high, and the mode line (MODE L)
is low. This causes the prescaler to divide by 17 (or 18, TRMODL=low). The mode line
stays low for 31-A counts, where A is the programmed number. The mode line goes
high, and the prescaler divides by 16 (or 17, TRMODL=low) for 31-N counts.
The total division is:
) + P*((31-N)-(31-A))
or
P*(31-N) + (31-A).
On the 31st count, the counters are reinitialized. Figure 6C-5 shows the timing of the
A-counter programmed to 26 and the N-counter programmed to 18, a total division of
213. Only the CKNL and MODEL signals shown in Figure 6C-4 are accessible at U62
pins 6 and 22, respectively.
6C-4
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