TROUBLESHOOTING AND REPAIR
FREQUENCY AND PHASE MODULATION
To prevent coincidence problems from occurring, an approaching coincidence
condition is detected with one part of the OVERLAP PULSE AND COINCIDENCE
detector, U19, using the divider outputs "RSIG" and "VSIG". The "RSIG" input
connects to the "D" input of a first D flip-flop and "V" connects to the clock input of
the same flip-flop. This sets up the flip-flop and Vckl/Vck2 switch, U18, so that the
second flip-flop, U19 will make an overlap pulse, clocked by signal "Vck1" and reset by
signal "Vck2" to drive the DAC least significant bits. The switch U18 causes the
up-down counter to use the second "V" clock ("Vck2" instead of "Vck1") for clocking,
causing a missing portion. The overlap pulse, which occurs at the time between the
"Vck1" and "Vck2" clock signals, just fills in for the missing portion. The smoothing
adjustment R88 is used to make up for inaccuracies of timing and lower order DAC bit
substitution.
The up-down counter is prevented from wrapping around from either high to low or
low to high by end-count detectors U48, p/o U10, and p/o U16 inverters, and
four-input NAND gates that control the appropriate clock inputs. This control
information is also used to determine overmodulation or an unlocked loop condition.
This information is passed to the uncal detector.
The uncal detector U20 receives these inputs and the inputs from the other phase
detector. When the phase detectors are close enough to the edge of normal operation,
this will trigger the uncal one-shot, U20, which will stretch out the time of abnormal
indication. The output, FM UNLCK, is sent to the instrument controller.
Following the phase detectors is the loop amplifier U25, which, in combination with
the analog switch, selects the appropriate phase detector and gain resistors, R66 and
R87, to control the phase-locked bandwidth. The circuit is followed by the loop filter,
which has rejection notches at 50 kHz, 90 kHz, and 200 kHz. This filter rejection
reduces the pulses from the phase detectors to maintain minimum spurious modulation
of the FM oscillator.
Also associated with the loop amplifier and loop filter are a comparator (U27) and a
relay (K4), which are used in DCFM mode of operation of the FM PCA.
The operation to enable DCFM is under control of the instrument controller. The
controller operation is as follows:
1. Set up normal ACFM, except disconnect input modulation signals.
2. Monitor comparator output, DCFMLO.
3. Adjust FM STEER DAC on Modulation Control PCA (All), using an
appropriate algorithm until the comparator senses nearly zero voltage at TP12.
Repeat as necessary.
4. When satisfied, assert the DCFMH control that closes the relay K4, puts TP12 at
0V DC ground, and disables dividers and phase lock, and disconnects phase
modulation path. The input modulation signals are reconnected through a DC
path.
ICs U29, U30, and U33 generate the control signals for the rest of the circuits for the
different ranges of modulation and the different modes of operation in FM, øM, and
DCFM. The inputs are the control lines from the instrument controller, and the
outputs control the divider, phase detector, oscillator, and modulation circuits. See the
Modulation Control Table (Table 6E-1) for the relationship.
6E-6
To Next Page
Loading...
