Fuji Electric RYS...S3-VVS Series - Origin LS (Limit Switch) Detection; LS-Z Pulse

MHT258a (Engl.)5-45
・Origin LS (limit switch) detection (40)
Because the origin LS signal requires quick response, this should be directly input to the amplifier in general. When the host controller
needs the origin signal, the origin LS detection signal can be output.
While the origin LS [LS] signal is on, the origin LS detection signal (40) is on.
・LS-Z pulse
The encoder pulse count from the time when the origin LS signal goes to OFF level until Z-phase signal is detected can be monitored.
[
]
If this count is small, Z-phase signal of one rotation later may have been detected, depending on the origin LS response. Move the
mechanical position of the origin LS.
Origin LS detection
Origin LS
APS30
APS30APS30
APS30
PWR
PWRPWR
PWR
ALM
ALMALM
ALM
ＳＸ
ＳＸＳＸ
ＳＸ
SCPU32
SCPU32SCPU32
SCPU32
LOADER
LOADERLOADER
LOADER
RUN
RUNRUN
RUN
TERM
TERMTERM
TERM
SLV
SLVSLV
SLV
STOP
STOPSTOP
STOP
CPU
CPUCPU
CPU
No.
No.No.
No.
ONL
ONLONL
ONL
ERR
ERRERR
ERR
RUN
RUNRUN
RUN
ALM
ALMALM
ALM
BAT
BATBAT
BAT
ONL01234567
ONL01234567ONL01234567
ONL01234567
ERR89101112131415
ERR89101112131415ERR89101112131415
ERR89101112131415
ONLCH1
ONLCH1ONLCH1
ONLCH1
ERRCH2
ERRCH2ERRCH2
ERRCH2
EMG+OT‑OT
EMG+OT‑OTEMG+OT‑OT
EMG+OT‑OT
20
2020
20
1
11
1
B/A
B/AB/A
B/A
HP2
HP2HP2
HP2
ONL
ONLONL
ONL
ERR
ERRERR
ERR
PE1
PE1PE1
PE1
PH
PHPH
PH
PL
PLPL
PL
DA
DADA
DA
CH
CHCH
CH
No.
No.No.
No.
SCPU32
SCPU32SCPU32
SCPU32
LOADER
LOADERLOADER
LOADER
RUN
RUNRUN
RUN
TERM
TERMTERM
TERM
SLV
SLVSLV
SLV
STOP
STOPSTOP
STOP
CPU
CPUCPU
CPU
No.
No.No.
No.
ONL
ONLONL
ONL
ERR
ERRERR
ERR
RUN
RUNRUN
RUN
ALM
ALMALM
ALM
BAT
BATBAT
BAT
ONL01234567
ONL01234567ONL01234567
ONL01234567
ERR89101112131415
ERR89101112131415ERR89101112131415
ERR89101112131415
K80791234
K80791234K80791234
K80791234
L1
L1L1
L1
L2
L2L2
L2
L3
L3L3
L3
DB
DBDB
DB
P1
P1P1
P1
N
NN
N
P+
P+P+
P+
U
UU
U
V
VV
V
W
WW
W
CHARGE
CHARGECHARGE
CHARGE
FALDIC
FALDICFALDIC
FALDIC
SHIFT
SHIFTSHIFT
SHIFT
ENT
ENTENT
ENT
RYS201S3-VVS
RYS201S3-VVSRYS201S3-VVS
RYS201S3-VVS
MODE
MODEMODE
MODE
ESC
ESCESC
ESC
K80791234
K80791234K80791234
K80791234
L1
L1L1
L1
L2
L2L2
L2
L3
L3L3
L3
DB
DBDB
DB
P1
P1P1
P1
N
NN
N
P+
P+P+
P+
U
UU
U
V
VV
V
W
WW
W
CHARGE
CHARGECHARGE
CHARGE
FALDIC
FALDICFALDIC
FALDIC
SHIFT
SHIFTSHIFT
SHIFT
ENT
ENTENT
ENT
RYS201S3-VVS
RYS201S3-VVSRYS201S3-VVS
RYS201S3-VVS
MODE
MODEMODE
MODE
ESC
ESCESC
ESC