Fuji Electric RYS...S3-VVS Series - 5.4 Position Control

MHT258a (Engl.)5-15
5.4 Position control
This section explains the signals related to position control using pulse train input.
Control input signal: Position control (37)
Pulse train ratio 1 (27)
Pulse train ratio 2 (28)
Deviation clear (50)
Position preset (16)
Current position output (56)
Control output signal: Deviation zero (23)
Deviation excessive
5.4.1 Position control
When this signal turns on, the amplifier enters the position control mode.
While the position control (37) signal turns on, the amplifier is in position control. Positioning using pulse train input, origin return and interrupt
positioning is available.
(1) Pulse train input
While pulse train ratio 1 (27) or 2 (28) is on, pulse train input is valid. (Position control (37) on is necessary.)
(2) Origin return
See 5.7 for origin return operation.
(3) Interrupt positioning
See 5.7 for interrupt positioning.
■ Interface
Position control
ON : In position control mode
OFF : In speed control mode
Pulse train ratio 1, 2
ON : Pulse train input is valid
OFF: Pulse train input is ignored
Pulse train input
Max. input frequency 400kHz
Pulse train
Position control (37)
Pulse train ratio 1 (27)
APS30
APS30APS30
APS30
PWR
PWRPWR
PWR
ALM
ALMALM
ALM
ＳＸ
ＳＸＳＸ
ＳＸ
SCPU32
SCPU32SCPU32
SCPU32
LOADER
LOADERLOADER
LOADER
RUN
RUNRUN
RUN
TERM
TERMTERM
TERM
SLV
SLVSLV
SLV
STOP
STOPSTOP
STOP
CPU
CPUCPU
CPU
No.
No.No.
No.
ONL
ONLONL
ONL
ERR
ERRERR
ERR
RUN
RUNRUN
RUN
ALM
ALMALM
ALM
BAT
BATBAT
BAT
ONL01234567
ONL01234567ONL01234567
ONL01234567
ERR89101112131415
ERR89101112131415ERR89101112131415
ERR89101112131415
ONLCH1
ONLCH1ONLCH1
ONLCH1
ERRCH2
ERRCH2ERRCH2
ERRCH2
EMG+OT‑OT
EMG+OT‑OTEMG+OT‑OT
EMG+OT‑OT
20
2020
20
1
11
1
B/A
B/AB/A
B/A
HP2
HP2HP2
HP2
ONL
ONLONL
ONL
ERR
ERRERR
ERR
PE1
PE1PE1
PE1
PH
PHPH
PH
PL
PLPL
PL
DA
DADA
DA
CH
CHCH
CH
No.
No.No.
No.
SCPU32
SCPU32SCPU32
SCPU32
LOADER
LOADERLOADER
LOADER
RUN
RUNRUN
RUN
TERM
TERMTERM
TERM
SLV
SLVSLV
SLV
STOP
STOPSTOP
STOP
CPU
CPUCPU
CPU
No.
No.No.
No.
ONL
ONLONL
ONL
ERR
ERRERR
ERR
RUN
RUNRUN
RUN
ALM
ALMALM
ALM
BAT
BATBAT
BAT
ONL01234567
ONL01234567ONL01234567
ONL01234567
ERR89101112131415
ERR89101112131415ERR89101112131415
ERR89101112131415
K80791234
K80791234K80791234
K80791234
L1
L1L1
L1
L2
L2L2
L2
L3
L3L3
L3
DB
DBDB
DB
P1
P1P1
P1
N
NN
N
P+
P+P+
P+
U
UU
U
V
VV
V
W
WW
W
CHARGE
CHARGECHARGE
CHARGE
FALDIC
FALDICFALDIC
FALDIC
SHIFT
SHIFTSHIFT
SHIFT
ENT
ENTENT
ENT
RYS201S3-VVS
RYS201S3-VVSRYS201S3-VVS
RYS201S3-VVS
MODE
MODEMODE
MODE
ESC
ESCESC
ESC
K80791234
K80791234K80791234
K80791234
L1
L1L1
L1
L2
L2L2
L2
L3
L3L3
L3
DB
DBDB
DB
P1
P1P1
P1
N
NN
N
P+
P+P+
P+
U
UU
U
V
VV
V
W
WW
W
CHARGE
CHARGECHARGE
CHARGE
FALDIC
FALDICFALDIC
FALDIC
SHIFT
SHIFTSHIFT
SHIFT
ENT
ENTENT
ENT
RYS201S3-VVS
RYS201S3-VVSRYS201S3-VVS
RYS201S3-VVS
MODE
MODEMODE
MODE
ESC
ESCESC
ESC
P24
M24
2.2k
+24V
470 × 3
P5
M5
AM26LS32