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Chapter 6: Solving Problems
Solving Target System Problems
31,30,29,28 set (0x0000000f), and the SYPCR register must have the
“Disable watchdog freeze” bit set (0x00000080).
If you see the “!ASYNC_STAT 173!” error
message
If after a break, the following error arises:
!ASYNC_STAT 173! MSR.RI bit not set - Break may not be recoverable
This indicates that the MSR.RI bit is not set, implying that a non-
maskable break was needed, and the interrupt may not be recoverable.
If this occurs while breaking out of regular code, then the MSR.RI bit
was not set in the boot code. This can be fixed by “ORing” in
0x00000002 into the SRR1 register and resuming the run.
If there are problems with the debug port
signals
❏ Check for pull-down resistors on DSDI and DSCK.
Some target systems may have 220 ohm pull-downs on these two
signals. These signals are series terminated by the analysis probe or
TIM with a 46 ohm resistor. A 220 ohm pull-down would present a 20%
drop in signal level when driven high, which could easily cause some
malfunctions. There should be a very weak pull-down on the target, if
any at all. If you want to pull-down DSCK, use a value of 2.2K or
greater.
To test the target system
The following program can be placed into memory.
start: addi r1,1 - 0x38210001
nop - 0x60000000
nop - 0x60000000
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