HP Series 37 - Page 117

Test Descriptions
SEP 84
3-2
I. Bit line errors: Any data bits that are in error for all registers tested will cause the
following
error message to be displayed:
Error in Step 4:
Bit line error.
bit a 4 8 12
v v v v
R8 0100 0000
R9 0000 0000 0100 0000
Rl0 0000 0000 0100 0000
2. Four-bit register errors: If data errors are limited to a four-bit section of a register, then
the following error message is displayed:
Error in Step 4:
Latch/buffer error.
bit a
4 8 12
v v v v
R8 0000 0000
R9 0000 1110 0000 0000
Rl0 0000 0000 0000 0000
3. Register select line errors: When one register fails the register test, the following error
message is displayed:
Error in Step 4:
Select line errors.
bit a 4 8
12
v v v v
R8 0000 0000
R9 1111 1111 1111 1111
Rl0 0000 0000 0000 0000
4. Handshake or write enable errors: If all registers fail without a discernible pattern, the
following error message is displayed:
Error in Step 4:
Check slave handshake
logic.
bit 0
4
8
12
v
v
v
y
R8
1101 1111
R9 1111
1011 1110
1101
Rl0 1101
1111 1111
0111