Test Descriptions
Step 28. DMA Termination Status Test -
•
00
- count and end
•
11
-
error
• 10 - count no end
•
01
- count subrecord
Step 29. DMA OBYTE Data Paths Test - Verifies
that
the LEFTOUT and RIGHTOUT registers
correctly unpack words
into
bytes.
Step 30. DMA IBYTE Data Paths Test - Verifies
that
the LEFTIN
and
RIGHTIN registers correctly
pack data bytes into words.
Step
32.
DMA Timeout Test - Verifies
that
the
DMA timeout abort functions correctly.
3.6
CSRQ
TEST
This test section verifies the correct operation of the channel request logic.
Step 33. Device Request Test - Verifies
that
DEVRQ
is
correctly asserted from each of the following
inputs:
• Parallel Poll
..
New Status
• CSRQDIS
•
DMINACT
• CIC
..
RIOC
..
OBSI
Step
34.
Channel Request Test - Verifies
that
CHANRQ
is
correctly asserted from each
of
the
following inputs:
• DMINT
•
PHIINT
• Parallel Poll
•
DMIN
D~.10FF
SEP 84
3-7
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