General
Information
This code tests
the
CPU chip and slow
WCS.
It
then loads the Code Loader and the second series of tests
into
Slow
WCS.
The second series of tests check additional portions of the CPU chip, fast
WCS,
and the CPU register file.
When these tests are successfully completed, the maintenance
panel code
is
loaded into
WCS
and enabled.
Then
the
Self Test Executive
is
loaded
into
WCS
and control
is
passed to it.
SELF
TEST
EXECUTIVE
The Self Test Executive determines
if
an
Auto Restart
after
power failure
is
to
be
performed. Auto
Restart
tests a subset
of
the memory tests.
If
a normal power--on sequence occurred, the Self Test Executive tests all
of
memory.
The
Self Test Executive
then
tests all of the
I/O
cards installed in
the
system
and
speed senses the system
console. The slot numbers
of
J
II
cards tested are displayed
elfi
the
console. The failing cards have the
error
code displayed in inverse video. A prompt
is
issued, unless
Auto
Warmstart
is
enabled. If Auto
Warmstart
is
specified, control
is
passed to the Loader Code and the
Autowarmstart
prompt
is
displayed.
POWER-ON
SELF
TEST
When power
is
applied
to
the
SPU,
the
executable ROM code loads
into
Writable Control Store
(WCS)
the
initial
part
of
Power On Self test (PON) and a ROM Code Loader. The code in
WCS
is
then
executed.
The basic
CPU
chip
test, a general
WCS
test, and a ROM code loader are in ROM. This code tests some of
the
Series
37
CPU
chip
functions. The last CPU chip function tested
is
all of Slow
WCS
and
then
additional CPU test modules
are
loaded. These modules test the remaining CPU chip functions. When
these tests are complete,
the
Maintenance Panel module, the Control module,
and
the Self Test Execntive
module
are
loaded. Control
is
then
passed to
the
Self Test Executive.
The
Test Executor loads
the
memory tests, the TIC test, and the PIC test. The memory tests are
then
executed.
If
the
memory tests are successfully executed, the console TIC
and
all of the
other
channels in
the
SPU
are
tested. The results
are
displayed on
the
LED display
and
the
console if speed sensing was
successful.
The
Control
module initializes
the
TIC and displays the following prompt:
H
for
help->
MAINTENANCE MODE
The
maintenance
mode microcode contains the code for
Maintenance
Mode, and Test Mode commands.
Unlike
earlier
version.
C'f
HP
~OOO
comrllters, there
is
no special
:nai!1ter..:l.I:cc
i'r~cessor.
The
maintenance
microcode resides on the CPU board. The Control B detection logic
is
enabled on
the
TIC
that
is
in slot I
channel
I
of
the
SPU card cage. Only the console connected to
Channell/Port
0 or the
remote console
can
issue Control B (Be) to
enter
Maintenance Mode.
NOV 84
1-2
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