HP Series 37 - Test Section 4; Alternating Ones and Zeros Test

Test Descriptions
3.4 TEST SECTION 4
Alternating Ones and Zeros Test
Step 41. Alternating Ones and Zeros Test -- This step writes an alternate one and zero pattern into all
available memory locations
in ascending address order and then reads them back. The
complement
pattern is then written and read back. The error latch is read after testing each
pattern to check whether any single bit errors were detected.
SEP 84
3-6
The following message will appear during test execution:
Begin Sect ion 4
Begin
Step 41
All of tested memory has been written
Pass 1 completed - Begin Pass 2
All of tested memory has been written
Step 41 completed
End of Section 4
The following error message will be displayed only if error correction is NOT working:
Expected: ~XXXXXX; Received: %yyyyyy
Address = ~ZZZZZZ
Bank = W
Board = A
Where: XXXXXX = data expected in octal
YYYYYY = data received in octal
ZZZZZZ '" address of error in octal 0 < = Z = 177777
W = bank with error 0 < = W < = 31
A = 0/1