Test Descriptions
3.8
TEST
SECTION 8
Low
Memory
Test
This section relocates
the
program
and
checks
the
memory
area
where
the
program
was originally located
(banks
0
and
I).
It
is
then
relocated back. This section will
NOT
respond to
the
Loop on
Error
option
and
does NOT provide
error
messages
until
the
last step
is
completed.
In
addition,
it
will NOT respond
to
CNTRL
V
or
any
other
type
of
I/O.
Step 81. Program Relocation
--
This step will relocate MDIAG37, DUS, stacks,
and
the
Device
Reference
Table (DRTS)
into
Banks 2
and
3
in
order
to test
the
area
in
lower
main
memory,
where
the
program was originally located.
Step 82. Marching Ones
and
Zeros
--
This step
is
identical
to
Step 71. These locations
are
written
and
read by
the
diagnostics.
Any
errors
are
recorded
in
the
error
latch. Because
of
limitationi
imposed by
the
relocation
of
the
diagnostic, only
the
last
error
encountered
by
the
marching
test
will be reported.
Step 83. Program
Re-Relocation
--
This step relocates
the
program
back
to
its original
area
in
lower
main
memory. The memory
status
is
checked
and
any
errors
that
were
encountered
in
the
marching
test (Step 82)
are
now displayed.
3.9
TEST
SECTION 9
This
text
section executes
only
upon exiting MDIAG.
Log
Test
Step 91. Log Test
--
This step will check
the
error
latch
to
make
sure
it
has been cleared before
the
diagnostic
returns
control
to DUS. This section will
NOT
respond to
the
Loop on
Error
option.
Error
message:
Single-bit
Error
Detected
Board: X
Syndrome Code:
%VVV
Chip Number:
UZZZZ
Where: X =
0/
I
YYY
= octal syndrome code
UZZZZ
= Reference Designator
of
faulty
RAM
SEP 84
3-11
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