Test Descriptions
3.2
IRQ
TEST
This test section verifies
the
correct operation
of
the PIC
Interrupt
Request logic.
Step
5.
Interrupt
Initialization Test - Verifies
that
the
interrupt
circuitry
is
initialized correctly.
Step
6.
Interrupt
Pending Register Test - Verifies
that
all eight INTPEN bits can
be
set and cleared.
Step
7.
Interrupt
Priority Encoder Test - Verifies
that
INTDEV is
the
highest priority
bit
set
in
the
INTPEN register.
Step
8.
Interrupt
Mask Bit Test - Verifies
that
MASKF can be set and cleared. MASKF
is
also tested
at
all channel addresses in the Channel Address Test Section.
Step
9.
Interrupt
Poll Test - Verifies
that
the
SIMB
IPOLL command functions. IPOLL uses
circuitry
shared with ROCL, SPOLL, IPOLL, and RMSKL. The shared circuitry
is
tested
at
all channel
addresses in
the
Channel Address Test section.
Step
10.
SIMB
Interrupt
Request Test - Verifies
that
the.
51MB
IRQ line functions.
3.3
CONFIGURATION
TEST
This section of
the
PICDIAG tests
the
correct operation
of
the PIC's Configuration Register bits.
Step
11.
Configuration Bits Zero Test - Tests all the configuration bits
in
t,heir zero state.
Step
12. Configuration Bits One Test - Tests all the configuration bits in
their
one state.
Step
13. Channel Address Test - The PICDIAG tests all possible channel addresses, except those
that
are
occupied by
other
channels on
the
SIMB.
At
each selected channel address, the channel
address decoder, registers
1 3 and 1
5,
and
the
global poll response are tested.
SEP 84
3-3
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