Test Descriptions
• Correct
error
and abort status.
• DMA
termination
status.
• Byte packing
and
unpacking.
Step
1 R DMA Initialization - Starts the DMA state machine and verifies
that
INIT resets the DMA
state machine to state
O.
Also checks
that
the
DMA state machine clocks
out
of state 0
after
writing
to
register
11.
Step
19.
CSRQ and
OBSI
Test - Verifies
that
at
state %
12
CHANRQ
is
asserted,
that
an
OBSI
causes
transition to state
0,
and
that
DMA machine stops in state
O.
Step
20.
DMA
Output
State Transitions verifies-
That
the
state machine
can
be
started
and
that
the
output
data
transfer
loops are
accessible.
If
either
of the data
transfer
loops are not accessible, the rest
of
the DMA
state
machine test aborts.
• The
output
transfer
loop (%20-%21-%23-%26-%27-%25) starting
at
both state
%20
and
state
%22.
• The end transitions
at
states
%23
and
%25.
•
That
a
data
transfer can
be
aborted
at
states
%21
and
%27.
Step
21.
DMA State Outputs Test - Verifies
the
outputs or
the
effects of the outputs for each state.
For
the
address and
count
register tests, a random number sequence
is
used to test different
combinations
of
starting address and count,
then
the DMA
is
run
to completion and the final
count
and address are verified.
Step
22.
DMA Input State Transitions verifies-
That
the
state machine can be started and
that
the input data
transfer
loops are
accessible.
If
either
of the data
transfer
loops are not accessible, the rest of the DMA
state machine test aborts.
• The
input
transfer loop (%1-%3-%14-%15-%17) starting
at
both state
%1
and state
%4
o The end transitions
at
states
%3
and % 1
7.
•
That
a data transfer can
be
aborted
at
states % 1 and % I
4.
Step
23.
DMCNT, DMADR Tests verifies-
•
That
the DMA byte counter logic functions correctly.
•
That
the DMA address register functions correctly.
Step
25.
DMA
Error
and Abort Test - Veriftes the address overfiow abort.
SEP 84
3-6
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