32 IBM System x3850 X6 and x3950 X6 Planning and Implementation Guide
Since data is moved using both channels at once, additional advanced memory protection
schemes can be implemented to provide protection against both single-bit and multi-bit
errors:
– Chipkill, also known as Single Device Data Correction (SDDC)
– Redundant Bit Steering (RBS)
The combination of these two RAS features is also known as Double Device Data
Correction (DDDC).
Mirroring and sparing are also supported in both modes as described in 2.4.2, “Memory
mirroring and rank sparing” on page 33.
Figure 2-24 shows the two modes. In RAS mode, both channels of one memory buffer are in
lockstep with each other.
Figure 2-24 Memory modes - Performance mode (left) and RAS mode (right)
Table 2-2 shows speed and maximum bandwidth for the SMI2 and DDR3 channels in both
modes.
Table 2-2 Memory mode comparison
Intel Xeon processor
DIMM
Memory
controller
DIMM
DIMM
Memory
controller
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
Memory
buffer
Memory
buffer
Memory
buffer
Memory
buffer
Data 1Data 0
Intel Xeon processor
DIMM
Memory
controller
DIMM
DIMM
Memory
controller
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
Memory
buffer
Memory
buffer
Memory
buffer
Memory
buffer
Data
Lockstep
channel
SMI2
links
DDR3
links
Memory performance mode Memory RAS mode
Bus Frequency Transfers/clock Transfer rate Data width Channel bandwidth
Performance mode
SMI2 Bus 1333 MHz 2 2666 MT/s 64 bit 21.3 GB/s
DDR3 Bus 667 MHz 2 1333 MT/s 64 bit 10.7 GB/s
RAS mode
SMI2 Bus 800 MHz 2 1600 MT/s 64 bit 12.8 GB/s
DDR3 Bus 800 MHz 2 1600 MT/s 64 bit 12.8 GB/s