36 IBM System x3850 X6 and x3950 X6 Planning and Implementation Guide
The following configuration rules apply for rank sparing:
Memory rank sparing is not supported if memory mirroring is enabled.
The spare rank must have identical or larger memory capacity than all the other ranks on
the same DDR3 channel.
When single-rank DIMMs are used, a minimum of two rank DIMMs must be installed per
memory channel to support memory sparing.
When multi-rank DIMMs are used, one multi-rank DIMM can be installed per memory
channel to support memory sparing.
The total memory available in the system is reduced by the amount of memory allocated
for the spare ranks.
2.4.3 Chipkill
Chipkill memory technology, an advanced form of error correction code (ECC) from IBM, is
available for the X6 servers. Chipkill (also known as Single Device Data Correction or SDDC)
protects the memory in the system from any single memory chip failure. It also protects
against multi-bit errors from any portion of a single memory chip.
Chipkill on its own is able to provide 99.94% memory availability to the applications without
sacrificing performance and with standard ECC DIMMs.
Chipkill is used in both Performance mode and RAS mode.
2.4.4 Redundant bit steering
Redundant bit steering provides the equivalent of a hot-spare drive in a RAID array. It is
based in the memory controller and senses when a chip on a DIMM fails and when to route
the data around the failed chip.
Redundant bit steering is only used in RAS mode.
Within the system, the models of the X6 servers using the Intel Xeon processor E7 v2 family
support the Intel implementation of Chipkill plus redundant bit steering, which Intel calls
Double Device Data Correction (DDDC).
Redundant bit steering uses the ECC coding scheme that provides Chipkill coverage for x4
DRAMs. This coding scheme leaves the equivalent of one x4 DRAM spare in every pair of
DIMMs. If a chip failure on the DIMM is detected, the memory controller can copy data from
the failed chip through the spare x4.
Redundant bit steering operates automatically without issuing a Predictive Failure Analysis
(PFA) or light path diagnostics alert to the administrator, although an event is logged to the
service processor log. In RAS (Lockstep) mode, after the second DRAM chip failure on the
DIMM, additional single bit errors will result in PFA and light path diagnostics alerts.
2.4.5 IBM Advanced Page Retire
Advanced Page Retire is an IBM unique algorithm to handle memory errors. It is a built-in
sophisticated error handling firmware that leverages and co-ordinates memory recovery
features, balancing the goals of maximum up time and minimum repair actions.
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