Intel Altera Agilex 7 - Page 53

Schematic Signal Name Description
SYS_LED3/D12
MAX_CONF_DONE for Avalon streaming configuration
SYS_LED5/D14
Reserved
SYS_LED7/D16
Reserved
SYS_PB0/S11
MAX_RESETn
SYS_PB1/S12
FPGA_RESETn
SYS_PB2/S14
Power recycle
SYS_PB3/S16
PGM_SEL for Avalon streaming configuration
SYS_PB4/S17
PGM_CFG for Avalon streaming configuration
FPGA_FAN_PWM
Fan 2 PWM signal
FPGA_FAN_TACH
Fan 2 tachometer signal
QSFP_RIGHT_FAN_PWM
Fan 3 PWM signal
QSFP_RIGHT_FAN_TACH
Fan 3 tachometer signal
QSFP_LEFT_FAN_PWM
Fan 1 PWM signal
QSFP_LEFT_FAN_TACH
Fan 1 tachometer signal
CORE_FETS_FAN_PWM
Fan 0 PWM signal
CORE_FETS_FAN_TACH
Fan 0 tachometer signal
MUX_SEL0
Mux Select for choosing either REFCLK_FGT_12A_8_DP/N
(or) REFCLK_FGT_12A_9_DP/N for FMCA_RECRD_CLK 0:
FMCA_RECRD_CLK= REFCLK_FGT_12A_8_DP/N 1:
FMCA_RECRD_CLK= REFCLK_FGT_12A_9_DP/N
MUX_SEL1
Mux select for choosing either REFCLK_FGT_13C_8_DP/N
(or) REFCLK_FGT_13C_9_DP/N for FMCB_RECRD_CLK 0:
FMCA_RECRD_CLK= REFCLK_FGT_13C_8_DP/N 1:
FMCA_RECRD_CLK= REFCLK_FGT_13C_9_DP/N
MCIO_CLK_SEL_EP_N
Tied to MUX_DIP_SW2
MCIO_CLK_ENN
Tied to MUX_DIP_SW3
MUX_DIP_SW0
DIP switch 0 signal (high by default)—tie this to MUX_SEL0
MUX_DIP_SW1
DIP switch 1 signal (high by default)—tie this to MUX_SEL1
MUX_DIP_SW2
MCIO_CLK_SEL_EP_NN:
Low before system power OK
High after system power OK
MUX_DIP_SW3
MCIO_CLK_ENN:
High before system power OK
Low after system power OK
VCCL_I2C_EN
Connect VCCL_SCL/SDA to system MAX 10 (Default:
ENABLE-1)
R_13C_PERST_IO_N
Driven low
R_13B_PERST_IO_N
Tied to MCIO PREST internally
R_12B_PERST_IO_N
Driven low
continued...
A. Development Kit Components
776646 | 2024.11.21
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7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
53