Intel Altera Agilex 7 - Page 54

Schematic Signal Name Description
R_12C_PERST_IO_N
Driven low
SI5395_1_A_IN_SEL0_R
Do not use (DNU)
SI5395_2_A_OEN_SYS_R
High before system power OK
Low after system power OK
SI52204_PWRGD_R
Tied to system power OK
SI5395_2_A_IN_SEL0_R
DNU
SI5395_1_A_OEN_SYS_R
High before system power OK
Low after system power OK
SI5391_A_OEN
High before system power OK
Low after system power OK
SI5391_A_RSTN
Low until system power OK
High after system power OK
SI5518_GPIO_0_R
DNU
CLK_OE_0_N
SI52204 CLK ENABLE0:
High before system power OK
Low after system power OK
CLK_OE_1_N
SI52204 CLK ENABLE1:
High before system power OK
Low after system power OK
CLK_OE_2_N
SI52204 CLK ENABLE2:
High before system power OK
Low after system power OK
SI5518_GPIO_1_R
DNU
SI5518_GPIO_2_R
DNU
CLK_SI5395_2_FINC_R
DNU
CLK_SI5395_2_FDEC_R
DNU
CLK_SI5395_1_FINC_R
DNU
CLK_SI5395_1_FDEC_R
DNU
SI5518_I2C_R_EN
Keep it enabled:
Low before system power OK
DNU after system power OK
R_12A_SPARE_N
Driven low
R_13A_SPARE_N
Driven low
DIMM_IO_R_EN
Enable always after system power OK
Low before system power OK
DNU after system power OK
FMC_B_PCIE_PERSTN_3V3
DNU
FMC_B_PCIE_WAKEN_3V3
DNU
FMC_A_PCIE_WAKEN_3V3
DNU
FMC_A_PCIE_PERSTN_3V3
DNU
A. Development Kit Components
776646 | 2024.11.21
Agilex
™
7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
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