Intel Altera Agilex 7 - Page 57

Schematic Signal Names Description
I2C_QSFP_2_SDA
I
2
C data
QSFPDD2_TX_[0:7]_DP/DN
Transceiver TX
QSFPDD2_RX_[0:7]_DP/DN
Transceiver RX
Table 16. QSFPDD Connector -3 (13B/J67)
Schematic Signal Names Description
QSFPDD3_3V3_MODPRS_L
Module present
QSFPDD3_3V3_RESET_L
Module reset
QSFPDD3_3V3_MODSEL_L
Mode select
QSFPDD3_3V3_LPMODE
Initial mode
QSFPDD3_3V3_INT_L
Interrupt
I2C_QSFP_2_SCL
I
2
C clock
I2C_QSFP_2_SDA
I
2
C data
QSFPDD3_TX_[0:7]_DP/DN
Transceiver TX
QSFPDD3_RX_[0:7]_DP/DN
Transceiver RX
QSFPDD800
Agilex 7 FPGA I-Series Transceiver Development Kit supports 1x QSFPDD800 port.
QSFPDD800 port fans out from the Agilex 7 I-Series FPGA F-Tile (FHT). The FHT Tile
from bank 12B and 12C can run up to 400 Gbps (50G x 8) PAM4 in DK-SI-AGI040FES.
4 FHT lanes from bank 12B+4 FHT lanes from bank 12C are terminated directly to
QSFPDD800 connector lanes [0:7] (J22).
Note: QSFPDD800 works up to 800 Gbps (100 G x 8) PAM4 in DK-SI-AGI040EA.
Table 17. QSFPDD800 (12B+12C)
Schematic Signal Names Description
QSFPDD800_MODPRS_L
Module present
QSFPDD800_RESET_L
Module reset
QSFPDD800_MODSEL_L
Mode select
QSFPDD800_LPMODE
Initial mode
QSFPDD800_INT_L
Interrupt
I2C_QSFP_1_SCL
I
2
C clock
I2C_QSFP_1_SDA
I
2
C data
QSFPDD800_TX_[0:7]_DP/DN
Transceiver TX
QSFPDD800_RX_[0:7]_DP/DN
Transceiver RX
A. Development Kit Components
776646 | 2024.11.21
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7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
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