Intel Altera Agilex 7 - Page 59

Schematic Signal Names Description
I2C_QSFP_2_SDA
I
2
C data
QSFP2_TX_[0:3]_DP/DN
Transceiver TX
QSFP2_RX_[0:3]_DP/DN
Transceiver RX
OSFP
Agilex 7 FPGA I-Series Transceiver Development Kit supports OSFP ports. OSFP port
fans out from the Agilex 7 I-Series FPGA F-Tile (FHT). The FHT Tile from bank 13B and
13C can run up to 400 Gbps (50G x 8) PAM4 in DK-SI-AGI040FES. 4 FHT lanes from
bank 13B + 4 FHT lanes from bank 13C are terminated directly to OSFP connector
lanes [0:7] (J45).
Note: OSFP works up to 800 Gbps (100G x 8) PAM4 in DK-SI-AGI040EA.
Table 21. OSFP (13B+13C)
Schematic Signal Names Description
OSFP_LPW_PRSNT_N
Initial mode/Module Present
OSFP_INT_RST_N
Interrupt/Reset
I2C_OSFP_3V3_SCL
I
2
C clock
I2C_OSFP_3V3_SDA
I
2
C data
OSFP_TX[0:7]_DP/DN
Transceiver TX
OSFP_RX[0:7]_DP/DN
Transceiver RX
SFP
Agilex 7 FPGA I-Series Transceiver Development Kit supports 4x SFP ports. SFP port
fans out from the Agilex 7 I-Series FPGA F-Tile (FGT). All 4 channels can run up to 1
Gbps/each SFP channel.
Table 22. SFP (12C/J77)
Schematic Signal Names Description
SFP3_TX_DISABLE Transmitter Disable
SFP3_RATE_SEL Module Rate Select 0
SFP3_MOD0_PRSNT_N Module Present
SFP3_LOS Loss of Signal
SFP3_TX_FAULT Transmitter Fault Indication
SFP3_RS1 Module rate select 1
SFP3_MOD0_SCL I
2
C clock
SFP3_MOD0_SDA I
2
C data
SFP3_TX_DP/DN Transceiver TX
SFP3_RX_DP/DN Transceiver RX
SFP2_TX_DISABLE Transmitter Disable
continued...
A. Development Kit Components
776646 | 2024.11.21
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7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
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