Serial Buses
SDM I/Os (SDM_IO0/12) and MAX 10 I/Os (VCCL_SDA/SCL) share the same I
2
C bus
which talks with Agilex 7 FPGA core regulators. By default, SDM acts as SmartVID
master and system MAX 10 act as Power GUI master in this chain.
System MAX 10 I/Os (PMB_SDA/SCL) manages the second I
2
C bus which access all
I
2
C slave regulators, except Agilex 7 FPGA core regulators.
System MAX 10 supports I
2
C master dedicated to clock related devices
(CLK_I2C_SDA/SCL), which manages 4# clock devices and SPI from Agilex 7 could
control SI5518 (clock device).
Agilex 7/System MAX 10 also manages QSFPDD800, 4x QSFPDD, 1DPC DIMM, 3x
QSFP, SFP, OSFP, 2x FMC, MCIO I
2
C buses System MAX 10 supports as a I
2
C Master
for Current (IVSNS_I2C_SDA /SCL) and Temperature sensors (T_SNS_SCL/SDA).
The SGPI Interface exists between System MAX 10 and Agilex 7 (FPGA_SGPIO_SYNC/
FPGA_SGPO/FPGA_SGPIO_CLK/FPGA_SGPI).
System MAX 10 as SPI Master to communicate with Agilex 7
(MAX10_SPI_SCLK/CSN/MOSI/MISO).
Agilex 7 as SPI Master to communicate with System MAX 10 (FPGA_SPI_SCLK/CSN/
MOSI/MISO).
Table 23. I
2
C Debug Headers
Schematic Signal Name Description
PMB_SCL/SDA
VRs I
2
C header J41
CLK_I2C_SDA/SCL_3V3
System MAX 10 Clock I
2
C bus header J140 (ES board) or
J42 (production board)
IVSNS_I2C_SDA /SCL
Current sensor J149
T_SNS_SCL/SDA
Temperature sensor I2C J79
Table 24. SPI Headers
Schematic Signal Name Description
SI5518_I2C_SCL_SCLK/SI5518_GPIO3_SDO/
SI5518_I2C_SDA_SDIO/SI5518_A0_CSB
SI5518 SPI Header J31
A. Development Kit Components
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7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
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